AT24C16B-.pdf

?1996 Microchip Technology Inc.DS21081D-page 1FEATURES?Single supply with operation from 4.5-5.5V?Low power CMOS technology-1 mA active current typical-10 A standby current typical at 5.5V?Organized as 4 or 8 blocks of 256 bytes(4 x 256 x 8)or(8 x 256 x 8)?2-wire serial interface bus,I2C?compatible?Schmitt trigger,?ltered inputs for noise suppres-sion?Output slope control to eliminate ground bounce?100 kHz compatibility?Self-timed write cycle(including auto-erase)?Page-write buffer for up to 16 bytes?2 ms typical write cycle time for page-write?Hardware write protect for entire memory?Can be operated as a serial ROM?ESD protection 4,000V?1,000,000 ERASE/WRITE cycles guaranteed?Data retention 200 years?8-pin DIP,8-lead or 14-lead SOIC packages?Available for extended temperature rangeDESCRIPTIONThe Microchip Technology Inc.24C08B/16B is an 8K or16K bit Electrically Erasable PROM intended for use inextended/automotive temperature ranges.The deviceis organized as four or eight blocks of 256 x 8-bit mem-ory with a 2-wire serial interface.The 24C08B/16B alsohas a page-write capability for up to 16 bytes of data.The 24C08B/16B is available in the standard 8-pin DIPand both 8-lead and 14-lead surface mount SOIC pack-ages.-Automotive(E):-40?Cto+125?CPACKAGE TYPESBLOCK DIAGRAMNCSSCCA0A1NCA2NCV1234567141312NCSCLSDANC981110WPVNC14-lead SOIC24C08B/16B24C08B/16BA0A1A2VSS12348765VCCWPSCLSDA24C08B/16BA0A1A2VSS12348765VCCWPSCLSDAPDIP8-leadSOICHV GENERATOREEPROM ARRAYPAGE LATCHESYDECXDECSENSE AMPR/W CONTROLMEMORYCONTROLLOGICI/OCONTROLLOGICWPSDASCLVCCVSS24C08B/16B8K/16K 5.0V I2C?Serial EEPROMsI2C is a trademark of Philips Corporation.This documentwascreatedwith FrameMaker4 0 4查询24C08 供应商24C08B/16BDS21081D-page 2?1996 Microchip Technology Inc.1.0ELECTRICAL CHARACTERISTICS1.1Maximum Ratings*VCC.7.0VAll inputs and outputs w.r.t.VSS.-0.6V to VCC+1.0VStorage temperature.-65?C to+150?CAmbient temp.with power applied.-65?C to+125?CSoldering temperature of leads(10 seconds).+300?CESD protection on all pins.4 kV*Notice:Stresses above those listed under“Maximum ratings”may cause permanent damage to the device.This is a stress rat-ing only and functional operation of the device at those or anyother conditions above those indicated in the operational listingsof this speci?cation is not implied.Exposure to maximum ratingconditions for extended periods may affect device reliability.TABLE 1-1:PIN FUNCTION TABLENameFunctionVSSGroundSDASerial Address/Data I/OSCL Serial ClockWPWrite Protect InputVCC+4.5V to 5.5V Power SupplyA0,A1,A2No Internal ConnectionTABLE 1-2:DC CHARACTERISTICSFIGURE 1-1:BUS TIMING START/STOPVCC=+4.5V to+5.5VAutomotive(E):Tamb=-40?C to+125?CParameterSymbolMinMaxUnitsConditionsWP,SCL and SDA pins:High level input voltageVIH.7 VccVLow Level input voltageVIL.3 VCCVHysteresis of Schmitt trigger inputsVHYS.05 VccV(Note)Low level output voltageVOL.40VIOL=3.0 mA,VCC=4.5VInput leakage currentILI-1010 AVIN=.1V to VCCOutput leakage currentILO-1010 AVOUT=.1V to VCCPin capacitance(all inputs/outputs)CIN,COUT10pFVCC=5.0V(Note 1)Tamb=25?C,FCLK=1 MHzOperating currentICC writeICC read31mAmAVCC=5.5V,SCL=400 kHzStandby currentICCS100 AVCC=5.5V,SDA=SCL=VCCNote:This parameter is periodically sampled and not 100%tested.TSU:STATHD:STAVHYSTSU:STOSTARTSTOPSCLSDA?1996 Microchip Technology Inc.DS21081D-page 324C08B/16BTABLE 1-3:AC CHARACTERISTICSFIGURE 1-2:BUS TIMING DATAParameterSymbolMinMaxUnitsRemarksClock frequencyFCLK100kHzClock high timeTHIGH4000nsClock low timeTLOW4700nsSDA and SCL rise timeTR1000ns(Note1)SDA and SCL fall timeTF300ns(Note 1)START condition hold timeTHD:STA4000nsAfter this period the?rst clock pulse is generatedSTART condition setup timeTSU:STA4700nsOnly relevant for repeated START conditionData input hold timeTHD:DAT0nsData input setup timeTSU:DAT250nsSTOP condition setup timeTSU:STO4000nsOutput valid from clockTAA3500ns(Note 2)Bus free timeTBUF4700nsTime the bus must be free before a new transmission can startOutput fall time from VIHmin to VIL maxTOF250ns(Note 1),CB 100 pFInput?lter spike suppres-sion(SDA and SCL pins)TSP50ns(Note 3)Write cycle timeTWR10msByte or Page modeEndurance24C08B24C16B1M10Mcycles25 C,VCC=5.0V,Block Mode(Note 4)Note 1:Not 100%tested.CB=total capacitance of one bus line in pF.2:As a transmitter,the device must provide an internal minimum delay time to bridge the unde?ned region(minimum 300 ns)of the falling edge of SCL to avoid unintended generation of START or STOP conditions.3:The combined TSP and VHYS speci?cations are due to new Schmitt trigger inputs which provide improved noise and spike suppression.This eliminates the need for a TI speci?cation.4:This parameter is not tested but guaranteed by characterization.For endurance estimates in a speci?c appli-cation,please consult the Total Endurance Model which can be obtained on our BBS or website.TSU:STATFTLOWTHIGHTRTHD:DATTSU:DATTSU:STOTHD:STATBUFTAATAATSPTHD:STASCLSDAINSDAOUT24C08B/16BDS21081D-page 4?1996 Microchip Technology Inc.2.0FUNCTIONAL DESCRIPTIONThe 24C08B/16B supports a Bi-directional 2-wire busand data transmission protocol.A device that sendsdata onto the bus is de?ned as transmitter,and a devicereceiving data as receiver.The bus has to be controlledby a master device which generates the serial clock(SCL),controls the bus access,and generates theSTART and STOP conditions,while the 24C08B/16Bworks as slave.Both,master and slave can operate astransmitter or receiver but the master device deter-mines which mode is activated.3.0BUS CHARACTERISTICSThe following bus protocol has been de?ned:?Data transfer may be initiated only when the bus is not busy.?During data transfer,the data line must remain stable whenever the clock line is HIGH.Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.Accordingly,the following bus conditions have beende?ned(Figure 3-1).3.1Bus not Busy(A)Both data and clock lines remain HIGH.3.2Start Data Transfer(B)A HIGH to LOW transition of the SDA line while theclock(SCL)is HIGH determines a START condition.Allcommands must be preceded by a START condition.3.3Stop Data Transfer(C)A LOW to HIGH transition of the SDA line while theclock(SCL)is HIGH determines a STOP condition.Alloperations must be ended with a STOP condition.3.4Data Valid(D)The state of the data line represents valid data when,after a START condition,the data line is stable for theduration of the HIGH period of the clock signal.The data on the line must be changed during the LOWperiod of the clock signal.There is one clock pulse perbit of data.Each data transfer is initiated with a START conditionand terminated with a STOP condition.The number ofthe data bytes transferred between the START andSTOP conditions is determined by the master deviceand is theoretically unlimited,although only the last 16will be stored when doing a write operation.When anoverwrite does occur it will replace data in a?rst in?rstout fashion.3.5AcknowledgeEach receiving device,when addressed,is obliged togenerate an acknowledge after the reception of eachbyte.The master device must generate an extra clockpulse which is associated with this acknowledge bit.The device that acknowledges,has to pull down theSDA line during the acknowledge clock pulse in such away that the SDA line is stable LOW during the HIGHperiod of the acknowledge related clock pulse.Ofcourse,setup and hold times must be taken intoaccount.During reads,a master must signal an end ofdata to the slave by NOT generating an acknowledgebit on the last byte that has been clocked out of theslave.In this case,the slave(24C08B/16B)will leavethe data line HIGH to enable the master to generate theSTOP condition.Note:The 24C08B/16B does not generate anyacknowledge bits if an internal program-ming cycle is in progress.FIGURE 3-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUS(A)(B)(D)(D)(A)(C)STARTCONDITIONADDRESS ORACKNOWLEDGEVALIDDATAALLOWEDTO CHANGESTOPCONDITIONSCLSDA?1996 Microchip Technology Inc.DS21081D-page 524C08B/16B3.6Device AddressingA control byte is the?rst byte received following thestart condition from the master device.The control byteconsists of a 4-bit control code,for the 24C08B/16B thisis set as 1010 binary for read and write operations.Thenext three bits of the control byte are the block selectbits(B2,B1,B0).They are used by the master deviceto select which of the eight 256 word blocks of memoryare to be accessed.These bits are in effect the threemost signi?cant bits of the word address.The last bit of the control byte de?nes the operation tobe performed.When set to one a read operation isselected,when set to zero a write operation is selected.Following the start condition,the 24C08B/16B monitorsthe SDA bus checking the device type identi?er beingtransmitted,upon a 1010 code the slave device outputsan acknowledge signal on the SDA line.Depending onthe state of the R/W bit,the 24C08B/16B will select aread or write operation.FIGURE 3-2:CONTROL BYTE ALLOCATIONOperationControl CodeBlock SelectR/WRead1010Block Address1Write1010Block Address0SLAVE ADDRESS1010B2B1B0R/WASTARTREAD/WRITE4.0WRITE OPERATION4.1Byte WriteFollowing the start condition from the master,thedevice code(4 bits),the block address(3 bits),and theR/W bit which is a logic low is placed onto the bus bythe master transmitter.This indicates to the addressedslave receiver that a byte with a word address will followafter it has generated an acknowledge bit during theninth clock cycle.Therefore the next byte transmitted bythe master is the word address and will be written intothe address pointer of the 24C08B/16B.After receivinganother acknowledge signal from the 24C08B/16B themaster device will transmit the data word to be writteninto the addressed memory location.The 24C08B/16Backnowledges again and the master generates a stopcondition.This initiates the internal write cycle,and dur-ing this time the 24C08B/16B will not generateacknowledge signals(Figure 4-1).4.2Page Write The write control byte,word address and the?rst databyte are transmitted to the 24C08B/16B in the sameway as in a byte write.But instead of generating a stopcondition the master transmits up to 16 data bytes tothe 24C08B/16B which are temporarily stored in the on-chip page buffer and will be written into the memoryafter the master has transmitted a stop condition.Afterthe receipt of each word,the four lower order addresspointer bits are internally incremented by one.Thehigher order seven bits of the word address remainsconstant.If the master should transmit more than 16words prior to generating the stop condition,theaddress counter will roll over and the previouslyreceived data will be overwritten.As with the byte writeoperation,once the stop condition is received an inter-nal write cycle will begin(Figure 4-2).FIGURE 4-1:BYTE WRITEFIGURE 4-2:PAGE WRITESPBUS ACTIVITYMASTERSDA LINEBUS ACTIVITYSTARTSTOPCONTROLBYTEWORDADDRESSDATAACKACKACKSPBUS ACTIVITYMASTERSDA LINEBUS ACTIVITYSTARTCONTROLBYTEWORDADDRESS(n)DATA nDATA n+15STOPACKACKACKACKACKDATA n+124C08B/16BDS21081D-page 6?1996 Microchip Technology Inc.5.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a writecycle,this can be used to determine when the cycle iscomplete(this feature can be used to maximize busthroughput).Once the stop condition for a write com-mand has been issued from the master,the device ini-tiates the internally timed write cycle.ACK polling canbe initiated immediately.This involves the master send-ing a start condition followed by the control byte for awrite command(R/W=0).If the device is still busy withthe write cycle,then no ACK will be returned.If thecycle is complete,then the device will return the ACKand the master can then proceed with the next read orwrite command.See Figure 5-1 for?ow diagram.FIGURE 5-1:ACKNOWLEDGE POLLING FLOW6.0WRITE PROTECTIONThe 24C08B/16B can be used as a serial ROM whenthe WP pin is connected to VCC.Programming will beinhibited and the entire memory will be write-protected.7.0READ OPERATIONRead operations are initiated in the same way as writeoperations with the exception that the R/W bit of theslave address is set to one.There are three basic typesof read operations:current address read,random read,and sequential read.SendWrite CommandSend StopCondition toInitiate Write CycleSend StartSend Control Bytewith R/W=0Did DeviceAcknowledge(ACK=0)?NextOperationNOYES7.1Current Address ReadThe 24C08B/16B contains an address counter thatmaintains the address of the last word accessed,inter-nally incremented by one.Therefore,if the previousaccess(either a read or write operation)was to addressn,the next current address read operation wouldaccess data from address n+1.Upon receipt of theslave address with R/W bit set to one,the 24C08B/16B issues an acknowledge and transmits the 8-bitdata word.The master will not acknowledge the transferbut does generate a stop condition and the 24C08B/16B discontinues transmission(Figure 7-1).7.2Random ReadRandom read operations allow the master to accessany memory location in a random manner.To performthis type of read operation,?rst the word address mustbe set.This is done by sending the word address to the24C08B/16B as part of a write operation.After the wordaddress is sent,the master generates a start conditionfollowing the acknowledge.This terminates the writeoperation,but not before the internal address pointer isset.Then the master issues the control byte again butwith the R/W bit set to a one.The 24C08B/16B will thenissue an acknowledge and transmits the 8-bit dataword.The master will not acknowledge the transfer butdoes generate a stop condition and the 24C08B/16Bdiscontinues transmission(Figure 7-2).7.3Sequential ReadSequential reads are initiated in the same way as a ran-dom read except that after the 24C08B/16B transmitsthe?rst data byte,the master issues an acknowledgeas opposed to a stop condition in a random read.Thisdirects the 24C08B/16B to transmit the next sequen-tially addressed 8 bit word(Figure 7-3).To provide sequential reads the 24C08B/16B containsan internal address pointer which is incremented byone at the completion of each operation.This addresspointer allows the entire memory contents to be seriallyread during one operation.7.4Noise ProtectionThe 24C08B/16B employs a VCC threshold detector cir-cuit which disables the internal erase/write logic if theVCC is below 1.5 volts at nominal conditions.The SCL and SDA inputs have Schmitt trigger and?ltercircuits which suppress noise spikes to assure properdevice operation even on a noisy bus.?1996 Microchip Technology Inc.DS21081D-page 724C08B/16BFIGURE 7-1:CURRENT ADDRESS READFIGURE 7-2:RANDOM READFIGURE 7-3:SEQUENTIAL READSPBUS ACTIVITYMASTERSDA LINEBUS ACTIVITYSTARTSTOPCONTROLBYTEDATA nACKNOACKSPSBUS ACTIVITYMASTERSDA LINEBUS ACTIVITYSTARTSTOPCONTROLBYTEACKWORDADDRESS(n)CONTROLBYTESTARTDATA(n)ACKACKNOACKPBUS ACTIVITYMASTERSDA LINEBUS ACTIVITYSTOPCONTROLBYTEACKNOACKDATA nDATA n+1DATA n+2DATA n+XACKACKACK8.0PIN DESCRIPTIONS8.1SDA Seria