FPGA串口通信.doc
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1、Four short words sum up what has lifted most successful individuals above the crowd: a little bit more.-author-dateFPGA串口通信FPGA串口通信FPGA实现RS-232串口收发的仿真过程(Quartus+Synplify+ModelSim)(2007-09-11 12:17:37) 网上关于RS-232的异步收发介绍得很多,最近没事学着摸索用ModelSim来做时序仿真,就结合网上的参考资料和自己的琢磨,做了这个东西。针对我这个小程序结合FPGA的开发流程,主要走了以下几步:1
2、. 文本程序输入(Verilog HDL)2. 功能仿真(ModelSim,查看逻辑功能是否正确,要写一个Test Bench)3. 综合(Synplify Pro,程序综合成网表)4. 布局布线(Quartus II,根据我选定的FPGA器件型号,将网表布到器件中,并估算出相应的时延)5. 时序仿真(ModelSim,根据时延做进一步仿真)这里贴出我的程序和各个详细步骤,能和各位正在学习的新手们一起分享。0. 原理略一、文本程序输入(Verilog HDL)发送端:module trans(clk, rst, TxD_start, TxD_data, TxD, TxD_busy );inpu
3、t clk, rst, TxD_start;input7:0 TxD_data; / 待发送的数据output TxD, / 输出端口发送的串口数据 TxD_busy;reg TxD;reg 7:0 TxD_dataReg; / 寄存器发送模式,因为在串口发送过程中输入端不可能一直保持有效电平reg 3:0 state;parameter ClkFrequency = 25000000; / 时钟频率25 MHzparameter Baud = 115200; / 串口波特率115200/ 波特率产生parameter BaudGeneratorAccWidth = 16;reg BaudGe
4、neratorAccWidth:0 BaudGeneratorAcc;wire BaudGeneratorAccWidth:0 BaudGeneratorInc = (Baud5)/(ClkFrequency4);wire BaudTick = BaudGeneratorAccBaudGeneratorAccWidth;wire TxD_busy;always (posedge clk or negedge rst) if(rst) BaudGeneratorAcc = 0;else if(TxD_busy) BaudGeneratorAcc = BaudGeneratorAccBaudGen
5、eratorAccWidth-1:0 + BaudGeneratorInc;/ 发送端状态wire TxD_ready = (state=0); / 当state = 0时,处于准备空闲状态,TxD_ready = 1assign TxD_busy = TxD_ready; / 空闲状态时TxD_busy = 0/ 把待发送数据放入缓存寄存器 TxD_dataRegalways (posedge clk or negedge rst) if(rst) TxD_dataReg = 8b00000000;else if(TxD_ready & TxD_start)TxD_dataReg = TxD
6、_data;/ 发送状态机always (posedge clk or negedge rst)if(rst) begin state = 4b0000; / 复位时,状态为0000,发送端一直发1电平 TxD = 1b1; endelsecase(state)4b0000: if(TxD_start) begin state = 4b0100; / 接受到发送信号,进入发送状态 end4b0100: if(BaudTick) begin state = 4b1000; / 发送开始位 - 0电平 TxD = 1b0; end4b1000: if(BaudTick) begin state =
7、 4b1001; / bit 0 TxD = TxD_dataReg0; end4b1001: if(BaudTick) begin state = 4b1010; / bit 1 TxD = TxD_dataReg1; end4b1010: if(BaudTick) begin state = 4b1011; / bit 2 TxD = TxD_dataReg2; end4b1011: if(BaudTick) begin state = 4b1100; / bit 3 TxD = TxD_dataReg3; end4b1100: if(BaudTick) begin state = 4b1
8、101; / bit 4 TxD = TxD_dataReg4; end4b1101: if(BaudTick) begin state = 4b1110; / bit 5 TxD = TxD_dataReg5; end4b1110: if(BaudTick) begin state = 4b1111; / bit 6 TxD = TxD_dataReg6; end4b1111: if(BaudTick) begin state = 4b0010; / bit 7 TxD = TxD_dataReg7; end4b0010: if(BaudTick) begin state = 4b0011;
9、 / stop1 TxD = 1b1; end4b0011: if(BaudTick) begin state = 4b0000; / stop2 TxD = 1b1; enddefault: if(BaudTick) begin state = 4b0000; TxD = 1b1; endendcaseendmodule接收端:module rcv(clk, rst, RxD, RxD_data, RxD_data_ready, );input clk, rst, RxD;output7:0 RxD_data; / 接收数据寄存器output RxD_data_ready; / 接收完8位数
10、据,RxD_data 值有效时,RxD_data_ready 输出读信号parameter ClkFrequency = 25000000; / 时钟频率25MHzparameter Baud = 115200; / 波特率115200reg2:0 bit_spacing;reg RxD_delay;reg RxD_start;reg3:0 state;reg7:0 RxD_data;reg RxD_data_ready;/ 波特率产生,使用8倍过采样parameter Baud8 = Baud*8;parameter Baud8GeneratorAccWidth = 16;wire Baud
11、8GeneratorAccWidth:0 Baud8GeneratorInc = (Baud88)/(ClkFrequency7);reg Baud8GeneratorAccWidth:0 Baud8GeneratorAcc;always (posedge clk or negedge rst) if(rst) Baud8GeneratorAcc = 0; else Baud8GeneratorAcc = Baud8GeneratorAccBaud8GeneratorAccWidth-1:0 + Baud8GeneratorInc;/ Baud8Tick 为波特率的8倍 115200*8 =
12、921600wire Baud8Tick = Baud8GeneratorAccBaud8GeneratorAccWidth;/ next_bit 为波特率 115200always (posedge clk or negedge rst)if(rst|(state=0) bit_spacing = 0;else if(Baud8Tick) bit_spacing = bit_spacing + 1;wire next_bit = (bit_spacing=7);/ 检测到 RxD 有下跳沿时,RxD_start 置1,准备接收数据always(posedge clk)if(Baud8Tick
13、)beginRxD_delay = RxD; RxD_start = (Baud8Tick & RxD_delay & (RxD);end/ 状态机接收数据always(posedge clk or negedge rst)if(rst) state = 4b0000;elseif(Baud8Tick) case(state) 4b0000: if(RxD_start) state = 4b1000; / 检测到下跳沿 4b1000: if(next_bit) state = 4b1001; / bit 0 4b1001: if(next_bit) state = 4b1010; / bit
14、1 4b1010: if(next_bit) state = 4b1011; / bit 2 4b1011: if(next_bit) state = 4b1100; / bit 3 4b1100: if(next_bit) state = 4b1101; / bit 4 4b1101: if(next_bit) state = 4b1110; / bit 5 4b1110: if(next_bit) state = 4b1111; / bit 6 4b1111: if(next_bit) state = 4b0001; / bit 7 4b0001: if(next_bit) state =
15、 4b0000; / 停止位 default: state = 4b0000; endcase/ 保存接收数据到 RxD_data 中always (posedge clk or negedge rst) if(rst) RxD_data = 8b00000000;else if(Baud8Tick & next_bit & state3)RxD_data = RxD, RxD_data7:1;/ RxD_data_ready 置位信号always (posedge clk or negedge rst) if(rst) RxD_data_ready = 0;else RxD_data_rea
16、dy = (Baud8Tick & next_bit & state=4b0001);endmodule为了测试收发是否正常,写的Test Benchtimescale 1ns / 1nsmodule rs232_test;reg clk, rst, TxD_start;reg 7:0 TxD_data;wire7:0RxD_data;wire /RxD, TxD, TxD_busy, RxD_data_ready;trans trans(.clk(clk), .rst(rst), .TxD_start(TxD_start), .TxD_busy(TxD_busy), .TxD_data(Tx
17、D_data), .TxD(TxD);rcv rcv(.clk(clk), .rst(rst), .RxD(TxD), / 收发相接时 RxD = TxD .RxD_data(RxD_data), .RxD_data_ready(RxD_data_ready); initialbeginTxD_start = 0; TxD_data = 0; clk = 0; rst = 1; #54 rst = 0; #70 rst = 1; #40 TxD_start = 1b1; #10 TxD_data = 8b11011001; #100 TxD_start = 1b0;endalways begi
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