01-微电子制造工艺流程.ppt
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1、电子工业专用设备,讲授内容,第一讲:微电子制造工艺流程(回顾) 第二讲:微电子制造装备概述 光刻工艺及基本原理 第三讲:光刻机结构及工作原理(1) 第四讲:光刻机结构及工作原理(2),本讲内容:CMOS工艺流程,录像:IC制造工艺 CMOS工作原理 CMOS工艺流程 IC工艺及其分类 IC制造厂的工艺分区,CMOS工作原理 (1),回顾录像:IC制造工艺,CMOS = Complementary Metal-Oxide-Semiconductor (Transistor) = 互补金属氧化物半导体(晶体管),N-MOS,P-MOS,n-well,p-well,CMOS工作原理 (2),N-MO
2、S电路 (1),Source = 源,Drain = 漏,Gate = 栅,p-type,n-type,n-type,Metal = 金属,Metal = 金属,CMOS工作原理 (3),N-MOS电路 (2),Source = 源,Drain = 漏,Gate = 栅,CMOS工作原理 (4),N-MOS电路 (3),Source = 源,Drain = 漏,Gate = 栅,CMOS工作原理 (5),N-MOS电路 (4),Source = 源,Drain = 漏,Gate = 栅,CMOS工作原理 (6),P-MOS电路 (1),Source = 源,Drain = 漏,Gate = 栅
3、,n-type,p-type,p-type,Metal = 金属,Metal = 金属,CMOS工作原理 (7),P-MOS电路 (2),Source = 源,Drain = 漏,Gate = 栅,CMOS工作原理 (8),P-MOS电路 (3),Source = 源,Drain = 漏,Gate = 栅,CMOS工艺流程,1. Shallow Trench Formation 2. Well Formation 3. Gate Formation 4. Source/Drain Formation,5. Salicide Formation 6. 1st Interconnect Layer
4、 7. 2nd through Nth Interconnect Layers 8. Passivation,4. P-MOS Source/Drain Formation,2. n-well formation,2. p-well formation,1. Trench Formation,3. Gate Formation,4. N-MOS Source/Drain Formation,5. Salicide Formation,6&7. Interconnect Layers,8. Passivation,N-MOS,P-MOS,Starting Point,Starting Point
5、: Pure silicon wafer (heavily-doped) with a lightly-doped epitaxial (Epi) layer. An Epi layer is used to provide a cleaner layer for device formation and to prevent “latch-up” of CMOS transistors.,Silicon Substrate P+,2 microns,725 microns,Silicon Epi Layer P-,Epitaxial = 外延淀积 or 外延生长,Shallow Trench
6、 Formation,Grow Pad Oxide: A very thin (200A) layer of silicon dioxide (SiO2) is grown on the surface by reacting silicon and oxygen at high temperatures. This will serve as a stress relief layer between the silicon and the subsequent nitride layer.,Silicon Substrate P+,Silicon Epi Layer P-,Pad Oxid
7、e,Thin Film = 薄膜,Deposit Silicon Nitride: A layer (2500A) of silicon nitride (Si3N4) is deposited using Chemical Vapor Deposition. This will serve as a polish stop layer during trench formation.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,CVD = Chemical Vapor Deposition = 化学气相淀积,Patter
8、n Photoresist for Definition of Trenches: One of the most critical patterning steps in the process. 0.5 - 1.0 microns of resist is spun, exposed, and developed.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,Photoresist,Trench = 沟槽,Patterning = 图形转移 Photoresist = 光刻胶 Expose = 曝光 Develop =
9、 显影,Etch Nitride and Pad Oxide: A reactive ion etch (RIE) utilizing fluorine chemistry is used.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,Photoresist,Etch = 刻蚀 RIE = Reactive Ion Etch = 反应离子刻蚀 Fluorine = 氟,Etch Trenches in Silicon: A reactive ion etch (RIE) utilizing fluorine chemist
10、ry is used. Defines transistor active areas.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,Photoresist,Transistor Active Areas,Isolation Trenches,Remove Photoresist: An oxygen plasma is used to burn off the resist layer.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,Transisto
11、r Active Areas,Isolation Trenches,Plasma = 等离子,Future PMOS Transistor,Future NMOS Transistor,Fill Trenches with Oxide: A CVD oxide layer is deposited to conformally fill the trenches. The oxide will prevent “cross-talk” between the transistors in the circuit.,Silicon Substrate P+,Silicon Epi Layer P
12、-,Silicon Nitride,Future PMOS Transistor,Silicon Dioxide,Future NMOS Transistor,No current can flow through here!,Polish Trench Oxide: The surface oxide is removed using a Chemical Mechanical Polish (CMP). The CMP process is designed to stop on silicon nitride.,Silicon Substrate P+,Silicon Epi Layer
13、 P-,Silicon Nitride,Future PMOS Transistor,Future NMOS Transistor,No current can flow through here!,Polish = 抛光 CMP = Chemical Mechanical Polish = 化学机械抛光,Remove Silicon Nitride: A wet etch in hot phosphoric acid (H3PO4) is used, completing formation of Shallow Trench Isolation (STI).,Silicon Substra
14、te P+,Silicon Epi Layer P-,Future PMOS Transistor,Future NMOS Transistor,Wet Etch = 湿法刻蚀,STI = Shallow Trench Isolation = 浅槽隔离,Well Formation,Pattern Photoresist for N-Well Formation: A non-critical masking layer, utilizing thicker resist to block the implant.,Silicon Substrate P+,Silicon Epi Layer
15、P-,Future PMOS Transistor,Future NMOS Transistor,Photoresist,N-Well = N阱,Implant N-Well: A deep (high-energy) implant of phosphorous ions creates a localized N-type region for the PMOS transistor.,Silicon Substrate P+,Silicon Epi Layer P-,Future NMOS Transistor,Photoresist,N- Well,Phosphorous (-) Io
16、ns,Ion Implantation = 离子注入,Strip N-Well Photoresist:,Silicon Substrate P+,Silicon Epi Layer P-,Future NMOS Transistor,N- Well,Strip = Remove = 去除,Photoresist,Pattern Photoresist for P-Well Formation: A non-critical masking layer, utilizing thicker resist to block the implant.,Silicon Substrate P+,Si
17、licon Epi Layer P-,Future NMOS Transistor,N- Well,Implant P-Well: A deep (high-energy) implant of boron ions creates a localized P-type region for the NMOS transistor.,Silicon Substrate P+,Silicon Epi Layer P-,Photoresist,N- Well,Boron (+) Ions,P- Well,Strip P-Well Photoresist:,Silicon Substrate P+,
18、Silicon Epi Layer P-,N- Well,P- Well,Anneal Well Implants: This step repairs damage to the silicon surface caused by the implants and electrically activates the dopants. It also drives the dopants somewhat deeper, but Rapid Thermal Processing is used to minimize dopant spreading.,Silicon Substrate P
19、+,Silicon Epi Layer P-,P- Well,N- Well,Anneal = 退火 RTP = Rapid Thermal Processing = 快速热处理 Dopant = 掺杂剂,Gate Formation,Grow Sacrificial Oxide: A thin (250A) oxide layer is grown to capture defects in the silicon surface.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Sacrificial Oxide,Sacr
20、ificial Oxide = 牺牲层氧化硅,Remove Sacrificial Oxide: Sacrificial oxide is immediately removed in a wet HF solution, leaving behind a clean silicon surface.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Grow Gate Oxide: This is the most critical step in the process! A very thin (20-100A) oxid
21、e layer is grown that will serve as the gate dielectric for both transistors. It must be extremely clean, and grown to a very precise thickness (+/- 1A).,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Deposit Polysilicon: Polycrystalline silicon is deposited using Chemical Vapor Depositio
22、n to a thickness of 1500-3000A.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Polysilicon,Polysilicon = Polycrystalline silicon = 多晶硅,Pattern Photoresist to Define Gate Electrodes: This is the most critical patterning step in the process! Precise sizing of the poly gate length is a first
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