ADN2913特性参数选型详解及样片.pdf
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1、ADNADN2 2913913 特性特性参数参数选型选型及及样片样片信息信息详解详解 SLICE ADJUST LOS THRESH TXD 11777-001 Data Recovery IC with Integrated Limiting Amp/EQ Data Sheet ADN2913 FEATURES Serial data input:6.5 Mbps to 8.5 Gbps No reference clock required Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance Qua
2、ntizer sensitivity:6.3 mV typical(limiting amplifier mode)Optional limiting amplifier,equalizer(EQ),and 0 dB EQ inputs Programmable jitter transfer bandwidth to support G.8251 OTN Programmable slice level Sample phase adjust(5.65 Gbps or greater)Output polarity invert Programmable LOS threshold via
3、I2C I2C interface to access optional features Loss of signal(LOS)alarm(limiting amplifier mode only)Loss of lock(LOL)indicator PRBS generator/detector Application-aware power 352 mW at 8.5 Gbps,equalizer mode,no clock output 380 mW at 6.144 Gbps,limiting amplifier mode,no clock output 340 mW at 622
4、Mbps,0 dB EQ mode,no clock output Power supplies:1.2 V,flexible 1.8 V to 3.3 V,and 3.3 V 4 mm 4 mm,24-lead LFCSP APPLICATIONS SONET/SDH OC-1/OC-3/OC-12/OC-48 and all associated FEC rates 1GE,1GFC,2GFC,4GFC,8GFC,CPRI OS/L.6 up to OS/L.60 Any rate regenerators/repeaters GENERAL DESCRIPTION The ADN2913
5、(样片申请信息查询:)provides the receiver functions of quantization,signal level detection,and clock and data recovery for continuous data rates from 6.5 Mbps to 8.5 Gbps.The ADN2913 automati-cally locks to all data rates without the need for an external reference clock or programming.ADN2913 jitter performa
6、nce exceeds all jitter specifications required by SONET/SDH,including jitter transfer,jitter generation,and jitter tolerance.The ADN2913 provides manual or automatic slice adjust and manual sample phase adjusts.Additionally,the user can select a limiting amplifier,equalizer,or 0 dB EQ at the input.T
7、he equalizer is adaptive or it can be manually set.The receiver front-end loss of signal(LOS)detector circuit indicates when the input signal level falls below a user-programmable threshold.The LOS detection circuit has hysteresis to prevent chatter at the LOS output.In addition,the input signal str
8、ength can be read through the I2C registers.The ADN2913 also supports pseudorandom binary sequence(PRBS)generation,bit error detection,and input data rate readback features.The ADN2913 is available in a compact 4 mm 4 mm,24-lead lead frame chip scale package(LFCSP).All ADN2913 specifica-tions are de
9、fined over the ambient temperature range of 40C to+85C,unless otherwise noted.FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN DATOUTP/CLKOUTP/SCK SDA LOL(OPTIONAL)DATOUTN CLKOUTN I2C_ADDR I2C REGISTERS FREQUENCY ACQUISITION AND LOCK DETECTOR ADN2913 DATA RATE CML CLK DDR CML LOS LOS DETECT SAMPLE PHASE ADJ
10、UST FIFO N 2 PIN NIN 50 VCM FLOAT 2 50 I2C VCC LA 0dB EQ EQ I2C DATA SAMPLER Figure 1.RXCK AND LOOP FILTER PHASE SHIFTER CLOCK Rev.0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable.However,no responsibilityis assumed by Analog Devices for its use,nor
11、 for anyinfringements of patents or other rightsofthird partiesthat may result fromitsuse.Specifications subjectto change without notice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarksandregisteredtrademarksarethepropertyoftheirrespect
12、iveowners.One Technology Way,P.O.Box 9106,Norwood,MA 02062-9106,U.S.A.Tel:781.329.4700 2013 Analog Devices,Inc.All rights reserved.Technical Support 国内外 65 家 IC 厂商免费样片查询:ICTry 样片申请网 Data Sheet Rev.0|Page 2 of 36 TABLE OF CONTENTS Features.1 Applications.1 General Description.1 Functional Block Diagr
13、am.1 Revision History.2 Specifications.3 Jitter Specifications.4 Output and Timing Specifications.6 Timing Diagrams.8 Absolute Maximum Ratings.9 Thermal Characteristics.9 ESD Caution.9 Pin Configuration and Function Descriptions.10 Typical Performance Characteristics.11 I2C Interface Timing and Inte
14、rnal Register Descriptions.13 Register Map.14 Theory of Operation.19 Functional Description.21 Frequency Acquisition.21 Limiting Amplifier.21 Slice Adjust.21 Edge Select.21 Loss of Signal(LOS)Detector.22 Passive Equalizer .23 0 dB EQ.23 Lock Detector Operation.24 Harmonic Detector.24 Output Disable
15、and Squelch.25 I2C Interface.25 Reference Clock(Optional).25 Additional Features Available via the I2C Interface.27 Input Configurations.29 Applications Information.32 Transmission Lines.32 Soldering Guidelines for Lead Frame Chip Scale Package.32 Outline Dimensions.33 Ordering Guide.33 REVISION HIS
16、TORY 12/13Revision 0:Initial Version Rev.0|Page 3 of 36 Data Sheet 国内外 65 家 IC 厂商免费样片查询:ICTry 样片申请网 SPECIFICATIONS TA=TMIN to TMAX,VCC=VCCMIN to VCCMAX,VCC1=VCC1MIN to VCC1MAX,VDD=VDDMIN to VDDMAX,VEE=0 V,input data pattern:PRBS 223 1,ac-coupled,I2C register default settings,unless otherwise noted.T
17、able 1.Parameter Test Conditions/Comments Min Typ Max Unit DATA RATE SUPPORT RANGE 0.0065 8.5 Gbps INPUTDC CHARACTERISTICS Peak-to-Peak Differential Input1 Input Resistance PIN NIN Differential 1.0 95 100 105 V 0 dB EQ PATHCML INPUT Input Voltage Range Input Common-Mode Level Differential Input Sens
18、itivity OC-48 8GFC2 At PIN or NIN,dc-coupled,RX_TERM_FLOAT=1(float)DC-coupled (see Figure 33),600 mV p-p differential,RX_TERM_FLOAT=1(float)Jitter tolerance scrambled pattern(JTSPAT),ac-coupled,RX_TERM_FLOAT=0(VCM=1.2 V),BER=1 1012 0.5 VCC 0.65 VCC 0.15 22 200 V V mV p-p mV p-p LIMITING AMPLIFIER IN
19、PUT PATH Differential Input Sensitivity OC-48 8GFC2 BER=1 1010 JTSPAT,BER=1 1012 6.3 8.3 mV p-p mV p-p EQUALIZER INPUT PATH Differential Input Sensitivity 8GFC2 15 inch FR-4,100 differential transmission line,adaptive equalizer(EQ)on JTSPAT,BER=1 1012 115 mV p-p INPUTAC CHARACTERISTICS S11 At 7.5 GH
20、z,differential return loss,see Figure 14 12 dB LOSS OF SIGNAL(LOS)DETECT Loss of Signal Detect Hysteresis(Electrical)LOS Assert Time LOS Deassert Time Loss of signal minimum program value Loss of signal maximum program value AC-coupled3 AC-coupled3 10 5 128 5.7 135 110 mV p-p mV p-p mV p-p dB s s LO
21、SS OF LOCK(LOL)DETECT DCO Frequency Error for LOL Assert DCO Frequency Error for LOL Deassert LOL Assert Response Time With respect to nominal,data collected in lock to reference(LTR)mode With respect to nominal,data collected in LTR mode 10.0 Mbps 2.5 Gbps 8.5 Gbps,JTSPAT 1000 250 10 51 25 ppm ppm
22、ms s s ACQUISITION TIME Lock to Data(LTD)Mode Optional LTR Mode 4 10.0 Mbps 2.5 Gbps 8.5 Gbps,JTSPAT 24 0.5 0.5 6.0 ms ms ms ms DATA RATE READBACK ACCURACY Coarse Readback Fine Readback In addition to reference clock accuracy 5 100%ppm Rev.0|Page 4 of 36 ADN2913 Data Sheet Parameter Test Conditions/
23、Comments Min Typ Max Unit POWER SUPPLY VOLTAGE VCC VDD VCC1 1.14 1.2 1.26 2.97 3.3 3.63 1.62 1.8 3.63 V V V POWER SUPPLY CURRENT VCC VDD VCC1 Limiting amplifier mode,clock output enabled 1.25 Gbps 3.125 Gbps 4.25 Gbps 6.144 Gbps 8GFC,2 JTSPAT 1.25 Gbps 3.125 Gbps 4.25 Gbps 6.144 Gbps 8GFC,2 JTSPAT 1
24、.25 Gbps 3.125 Gbps 4.25 Gbps 6.144 Gbps 8GFC,2 JTSPAT 277.1 311.0 256.2 288.3 270.1 304.0 303.1 340.4 319.1 359.5 7.24 8.28 7.21 8.21 7.23 8.33 7.26 8.17 7.20 8.1 35.6 46.8 19.0 24.1 22.2 28.2 19.4 24.6 22.2 28.4 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA TOTAL POWER DISSIPATION Clock Output Enab
25、led Clock Output Disabled Limiting amplifier mode,1.25 Gbps Limiting amplifier mode,3.125 Gbps Limiting amplifier mode,4.25 Gbps Limiting amplifier mode,6.144 Gbps Limiting amplifier mode,8GFC,2 JTSPAT Equalizer mode,8.5 Gbps Limiting amplifier mode,6.144 Gbps 0 dB EQ mode,622 Mbps 420.4 365.5 388 4
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