《高性能处理器》PPT课件.ppt
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1、取指和取数都要访问同一个存储器取指和取数都要访问同一个存储器Detection is easy in this case!(right half highlight means read,left half write)MemInstr.OrderTime(clock cycles)LoadInstr 1Instr 2Instr 3Instr 4ALUMemRegRegALUMemRegMemRegALUMemRegMemRegALURegMemRegALUMemRegMemRegMem结构相关:由访存引起的结构相关结构相关:由访存引起的结构相关2023/1/141USTC CS AN Hon
2、g取指延迟一拍进行取指延迟一拍进行MemInstr.OrderTime(clock cycles)LoadInstr 1Instr 2Instr 3Instr 4ALUMemRegRegALUMemRegMemRegALUMemRegMemRegALURegMemRegALUMemRegMemRegMemStall结构相关的解决方案:阻塞结构相关的解决方案:阻塞2023/1/142USTC CS AN Hong控制相关:控制相关:Whats the Problem?Instruction FetchDecodeExecuteMemory AccessWritebackNeed address
3、hereCompute address hereBranch Delaybne r2,#0,r3add r4,r5,r6sub r7,r8,r9TNT例:例:BEQ rs,rt,offset if Rrs=Rrt then PC -尽快尽快获得转移的目标地址(分支地址相关)获得转移的目标地址(分支地址相关)2023/1/143USTC CS AN HongnStall:wait until decision is clearnImpact:2 lost cycles(i.e.3 clock cycles per branch instruction)=slownMove decision to
4、 end of decodesave 1 cycle per branchInstr.OrderTime(clock cycles)AddBeqLoadALUMemRegMemRegALUMemRegMemRegALURegMemRegMemLostpotentialControl Hazard Solution#1:Stall2023/1/144USTC CS AN HongnPredict:guess one direction then back up if wrongnImpact:0 lost cycles per branch instruction if right,1 if w
5、rong(right 50%of time)nMore dynamic scheme:history of 1 branch(90%)Instr.OrderTime(clock cycles)AddBeqLoadALUMemRegMemRegALUMemRegMemRegMemALURegMemRegControl Hazard Solution#2:Predict2023/1/145USTC CS AN HongnDelayed Branch:Redefine branch behavior(takes place after next instruction)nImpact:0 clock
6、 cycles per branch instruction if can find instruction to put in“slot”(50%of time)nAs launch more instruction per clock cycle,less usefulInstr.OrderTime(clock cycles)AddBeqMiscALUMemRegMemRegALUMemRegMemRegMemALURegMemRegLoadMemALURegMemRegControl Hazard Solution#3:Delayed Branch2023/1/146USTC CS AN
7、 HongI:add r1,r2,r3J:sub r4,r1,r3Data Hazard on R1nRead After Write(RAW)InstrJ tries to read operand before InstrI writes itnCaused by a“Dependence”(in compiler nomenclature).This hazard results from an actual need for communication.2023/1/147USTC CS AN Hongadd r1,r2,r3sub r4,r1,r3and r6,r1,r7or r8,
8、r1,r9xor r10,r1,r11Data Hazard on r1:Read after write hazard(RAW)2023/1/148USTC CS AN HongInstr.OrderTime(clock cycles)add r1,r2,r3sub r4,r1,r3and r6,r1,r7or r8,r1,r9xor r10,r1,r11IFID/RFEXMEMWBALUImRegDmRegALUImRegDmRegALUImRegDmRegImALURegDmRegALUImRegDmRegData Hazard on r1:Read after write hazard
9、(RAW)nDependencies backwards in time are hazards2023/1/149USTC CS AN HongInstr.OrderTime(clock cycles)add r1,r2,r3sub r4,r1,r3and r6,r1,r7or r8,r1,r9xor r10,r1,r11IFID/RFEXMEMWBALUImRegDmRegALUImRegDmRegALUImRegDmRegImALURegDmRegALUImRegDmRegData Hazard Solution:Forwardingn“Forward”result from one s
10、tage to another2023/1/1410USTC CS AN HongRegTime(clock cycles)lw r1,0(r2)sub r4,r1,r3IFID/RFEXMEMWBALUImRegDmALUImRegDmRegForwarding(or Bypassing):What about Loads?nDependencies backwards in time are hazardsnData Hazard Even with ForwardingnCant solve with forwarding,Must delay/stall instruction dep
11、endent on loads2023/1/1411USTC CS AN HongRegTime(clock cycles)lw r1,0(r2)sub r4,r1,r3IFID/RFEXMEMWBALUImRegDmALUImRegDmRegStallForwarding(or Bypassing):What about Loads?nDependencies backwards in time are hazardsnData Hazard Even with ForwardingnCant solve with forwarding,Must delay/stall instructio
12、n dependent on loads2023/1/1412USTC CS AN HongTry producing fast code fora=b+c;d=e f;assuming a,b,c,d,e,and f in memory.Slow code:LW Rb,bLW Rc,cADD Ra,Rb,RcSW a,Ra LW Re,e LW Rf,fSUB Rd,Re,RfSWd,RdSoftware Scheduling to Avoid Load HazardsFast code:LW Rb,bLW Rc,cLW Re,e ADD Ra,Rb,RcLW Rf,fSW a,Ra SUB
13、 Rd,Re,RfSWd,RdCompiler optimizes for performance.Hardware checks for safety.2023/1/1413USTC CS AN HongData Hazard Solution(3):OutofOrder ExecutionnNeed to detect data dependences at run timenNeed of precise exceptions:Outoforder execution,inorder completion Time T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T
14、12sub$2,$1,$3 IF ID EX ME WBadd$14,$5,$4 IF ID EX ME WB sw$15,100($6)IF ID EX ME WB and$12,$2,$3 IF *ID EX ME WBor$13,$6,$2 IF ID EX ME WB2023/1/1414USTC CS AN HongData Hazard Solution(4):Data SpeculationnIn a wideissue processors,e.g.8 12 instructions per clock cycleLarger than a basic block(5 7 in
15、structions)Multiple branches use multiplebranch prediction(e.g.trace cache)Multiple data dependence chains very hard to execute them in the same clock cyclenValue speculation is primarily used to resolve data dependences:In the same clock cycleLong latency operations(e.g.load operations)2023/1/1415U
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