01-微电子制造工艺流程.ppt

电子工业专用设备,讲授内容,第一讲：微电子制造工艺流程（回顾） 第二讲：微电子制造装备概述 光刻工艺及基本原理 第三讲：光刻机结构及工作原理(1) 第四讲：光刻机结构及工作原理(2),本讲内容：CMOS工艺流程,录像：IC制造工艺 CMOS工作原理 CMOS工艺流程 IC工艺及其分类 IC制造厂的工艺分区,CMOS工作原理 (1),回顾录像：IC制造工艺,CMOS = Complementary Metal-Oxide-Semiconductor (Transistor) = 互补金属氧化物半导体（晶体管）,N-MOS,P-MOS,n-well,p-well,CMOS工作原理 (2),N-MOS电路 (1),Source = 源,Drain = 漏,Gate = 栅,p-type,n-type,n-type,Metal = 金属,Metal = 金属,CMOS工作原理 (3),N-MOS电路 (2),Source = 源,Drain = 漏,Gate = 栅,CMOS工作原理 (4),N-MOS电路 (3),Source = 源,Drain = 漏,Gate = 栅,CMOS工作原理 (5),N-MOS电路 (4),Source = 源,Drain = 漏,Gate = 栅,CMOS工作原理 (6),P-MOS电路 (1),Source = 源,Drain = 漏,Gate = 栅,n-type,p-type,p-type,Metal = 金属,Metal = 金属,CMOS工作原理 (7),P-MOS电路 (2),Source = 源,Drain = 漏,Gate = 栅,CMOS工作原理 (8),P-MOS电路 (3),Source = 源,Drain = 漏,Gate = 栅,CMOS工艺流程,1. Shallow Trench Formation 2. Well Formation 3. Gate Formation 4. Source/Drain Formation,5. Salicide Formation 6. 1st Interconnect Layer 7. 2nd through Nth Interconnect Layers 8. Passivation,4. P-MOS Source/Drain Formation,2. n-well formation,2. p-well formation,1. Trench Formation,3. Gate Formation,4. N-MOS Source/Drain Formation,5. Salicide Formation,6&7. Interconnect Layers,8. Passivation,N-MOS,P-MOS,Starting Point,Starting Point: Pure silicon wafer (heavily-doped) with a lightly-doped epitaxial (Epi) layer. An Epi layer is used to provide a cleaner layer for device formation and to prevent “latch-up” of CMOS transistors.,Silicon Substrate P+,2 microns,725 microns,Silicon Epi Layer P-,Epitaxial = 外延淀积 or 外延生长,Shallow Trench Formation,Grow Pad Oxide: A very thin (200A) layer of silicon dioxide (SiO2) is grown on the surface by reacting silicon and oxygen at high temperatures. This will serve as a stress relief layer between the silicon and the subsequent nitride layer.,Silicon Substrate P+,Silicon Epi Layer P-,Pad Oxide,Thin Film = 薄膜,Deposit Silicon Nitride: A layer (2500A) of silicon nitride (Si3N4) is deposited using Chemical Vapor Deposition. This will serve as a polish stop layer during trench formation.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,CVD = Chemical Vapor Deposition = 化学气相淀积,Pattern Photoresist for Definition of Trenches: One of the most critical patterning steps in the process. 0.5 - 1.0 microns of resist is spun, exposed, and developed.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,Photoresist,Trench = 沟槽,Patterning = 图形转移 Photoresist = 光刻胶 Expose = 曝光 Develop = 显影,Etch Nitride and Pad Oxide: A reactive ion etch (RIE) utilizing fluorine chemistry is used.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,Photoresist,Etch = 刻蚀 RIE = Reactive Ion Etch = 反应离子刻蚀 Fluorine = 氟,Etch Trenches in Silicon: A reactive ion etch (RIE) utilizing fluorine chemistry is used. Defines transistor active areas.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,Photoresist,Transistor Active Areas,Isolation Trenches,Remove Photoresist: An oxygen plasma is used to burn off the resist layer.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,Transistor Active Areas,Isolation Trenches,Plasma = 等离子,Future PMOS Transistor,Future NMOS Transistor,Fill Trenches with Oxide: A CVD oxide layer is deposited to conformally fill the trenches. The oxide will prevent “cross-talk” between the transistors in the circuit.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,Future PMOS Transistor,Silicon Dioxide,Future NMOS Transistor,No current can flow through here!,Polish Trench Oxide: The surface oxide is removed using a Chemical Mechanical Polish (CMP). The CMP process is designed to stop on silicon nitride.,Silicon Substrate P+,Silicon Epi Layer P-,Silicon Nitride,Future PMOS Transistor,Future NMOS Transistor,No current can flow through here!,Polish = 抛光 CMP = Chemical Mechanical Polish = 化学机械抛光,Remove Silicon Nitride: A wet etch in hot phosphoric acid (H3PO4) is used, completing formation of Shallow Trench Isolation (STI).,Silicon Substrate P+,Silicon Epi Layer P-,Future PMOS Transistor,Future NMOS Transistor,Wet Etch = 湿法刻蚀,STI = Shallow Trench Isolation = 浅槽隔离,Well Formation,Pattern Photoresist for N-Well Formation: A non-critical masking layer, utilizing thicker resist to block the implant.,Silicon Substrate P+,Silicon Epi Layer P-,Future PMOS Transistor,Future NMOS Transistor,Photoresist,N-Well = N阱,Implant N-Well: A deep (high-energy) implant of phosphorous ions creates a localized N-type region for the PMOS transistor.,Silicon Substrate P+,Silicon Epi Layer P-,Future NMOS Transistor,Photoresist,N- Well,Phosphorous (-) Ions,Ion Implantation = 离子注入,Strip N-Well Photoresist:,Silicon Substrate P+,Silicon Epi Layer P-,Future NMOS Transistor,N- Well,Strip = Remove = 去除,Photoresist,Pattern Photoresist for P-Well Formation: A non-critical masking layer, utilizing thicker resist to block the implant.,Silicon Substrate P+,Silicon Epi Layer P-,Future NMOS Transistor,N- Well,Implant P-Well: A deep (high-energy) implant of boron ions creates a localized P-type region for the NMOS transistor.,Silicon Substrate P+,Silicon Epi Layer P-,Photoresist,N- Well,Boron (+) Ions,P- Well,Strip P-Well Photoresist:,Silicon Substrate P+,Silicon Epi Layer P-,N- Well,P- Well,Anneal Well Implants: This step repairs damage to the silicon surface caused by the implants and electrically activates the dopants. It also drives the dopants somewhat deeper, but Rapid Thermal Processing is used to minimize dopant spreading.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Anneal = 退火 RTP = Rapid Thermal Processing = 快速热处理 Dopant = 掺杂剂,Gate Formation,Grow Sacrificial Oxide: A thin (250A) oxide layer is grown to capture defects in the silicon surface.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Sacrificial Oxide,Sacrificial Oxide = 牺牲层氧化硅,Remove Sacrificial Oxide: Sacrificial oxide is immediately removed in a wet HF solution, leaving behind a clean silicon surface.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Grow Gate Oxide: This is the most critical step in the process! A very thin (20-100A) oxide layer is grown that will serve as the gate dielectric for both transistors. It must be extremely clean, and grown to a very precise thickness (+/- 1A).,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Deposit Polysilicon: Polycrystalline silicon is deposited using Chemical Vapor Deposition to a thickness of 1500-3000A.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Polysilicon,Polysilicon = Polycrystalline silicon = 多晶硅,Pattern Photoresist to Define Gate Electrodes: This is the most critical patterning step in the process! Precise sizing of the poly gate length is a first-order determinant of transistor switching speed. The highest-technology patterning systems are used (i.e. DUV) along with thinner-than-normal photoresist due to the critical nature of the layer.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Photoresist,Channel Length,Polysilicon,DUV = Deep Ultra Violet = 深紫外,Etch Polysilicon and Strip Resist: Reactive Ion Etching using fluorine chemistry is used. This completes the formation of the “gate stack.”,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Oxidize Polysilicon: A thin layer of oxide is grown on top of the polysilicon to act as a buffer between the poly and the subsequent silicon nitride layer.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Gate Oxide,Poly Gate Electrode,Poly Re-oxidation,Source/Drain Formation,Pattern Photoresist for NMOS Transistor Tip Implant:,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Photoresist,NMOS Transistor Tip Implant: A very shallow (low energy) and low dose implant of arsenic ions begins the formation of the NMOS transistor source and drain. The “tip” will serve to reduce hot electron effects near the gate region.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Photoresist,Arsenic (-) Ions,N Tip,Strip Photoresist:,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N Tip,Pattern Photoresist for PMOS Transistor Tip Implant:,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Photoresist,N Tip,PMOS Transistor Tip Implant: A very shallow (low energy) and low dose implant of BF2 ions begins the formation of the PMOS transistor source and drain. The “tip” will serve to reduce hot electron effects near the gate region.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Photoresist,BF2 (+) Ions,N Tip,P Tip,Strip Photoresist:,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N Tip,P Tip,Deposit Silicon Nitride Layer: Using Chemical Vapor Deposition, thickness 1200-1800A.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Silicon Nitride,Thinner Here,Thicker Here,N Tip,P Tip,Etch Nitride to Form Spacer Sidewalls: Using a carefully controlled RIE etch, the thin nitride is removed from the horizontal surfaces, but the sidewalls remain. These sidewalls will precisely position the implants that form the transistor sources and drains.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Spacer Sidewall,N Tip,P Tip,Sidewall = 侧墙,Pattern Photoresist for NMOS Transistor Source/Drain Implant:,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Photoresist,N Tip,P Tip,NMOS Transistor Source/Drain Implant: A shallow and high-dose implant of arsenic ions completes the formation of the heavily-doped NMOS transistor source and drain. The spacer shadows the implant near the gate region.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,Photoresist,Arsenic (-) Ions,N+ Source,N+ Drain,P Tip,Strip Photoresist:,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P Tip,Pattern Photoresist for PMOS Transistor Source/Drain Implant:,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,Photoresist,P Tip,PMOS Transistor Source/Drain Implant: A shallow and high-dose implant of BF2 ions completes the formation of the heavily-doped PMOS transistor source and drain. The spacer shadows the implant near the gate region.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,BF2 (+) Ions,Photoresist,N+ Source,N+ Drain,P+ Drain,P+ Source,Strip Photoresist and Anneal Implants: Use Rapid Thermal Annealing to virtually eliminate dopant migration in the shallow source and drains. The electronic devices are now completely formed. All that remains is to connect them together.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P+ Drain,P+ Source,Lightly Doped “Tips”,Salicide Formation,Strip Surface Oxides: A quick dip in HF to expose bare silicon in the source, gate, and drain areas.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P+ Source,P+ Drain,Salicide = 准金属硅化物,Deposit Titanium: Use a sputterer to deposit a thin (200-400A) layer of titanium across the entire wafer surface.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P+ Source,P+ Drain,Titanium,Sputter = 溅射 PVD = Physical Vapor Deposition = 物理气相淀积 Titanium = 钛,Titanium Silicide Formation: Rapid Thermal Processing in nitrogen at 800C causes the titanium to react with silicon, forming titanium silicide, where the two are in contact. In other areas, the titanium is unchanged. This process perfectly aligns the silicide to the exposed silicon, and is called Self-Aligned Silicide, or Salicide.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P+ Source,P+ Drain,Titanium Silicide,Unreacted Titanium,Titanium Etch: The unreacted titanium is removed using a wet etch in NH4OH + H2O2. The titanium silicide remains. TiSi2 provides an ohmic contact between silicon and metal.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P+ Source,P+ Drain,Titanium Silicide,Ohmic Contact = 电阻接触,1st Interconnect Layer,Deposit BPSG: Silicon dioxide doped with small amounts of boron and phosphorous to enable film reflow and to getter contaminants is deposited using Chemical Vapor Deposition. Approximate thickness is 1 micron. This layer will electrically insulate the devices from the 1st metal layer.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P+ Source,P+ Drain,BPSG,Interconnect = 互连,BPSG = Borophosphosilicate Glass = 硼磷硅玻璃,Polish BPSG: Use Chemical Mechanical Polishing to achieve a flat surface on the BPSG layer. If not removed, the bumps on the surface from the underlying topography would cause a problem for the subsequent photolithography steps and degrade metal step coverage.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P+ Source,P+ Drain,BPSG,Photolithography = 光刻,Pattern Photoresist to Define Contacts: Contacts are openings in the BPSG layer enabling electrical access to the devices below. This is a critical photolithography step.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P+ Source,P+ Drain,BPSG,Photoresist,Contact = 接触孔,Contact Etch: A carefully designed RIE etch using fluorine chemistry to achieve vertical sidewalls.,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P+ Source,P+ Drain,BPSG,Photoresist,Strip Photoresist:,Silicon Substrate P+,Silicon Epi Layer P-,P- Well,N- Well,N+ Source,N+ Drain,P+ Source,P+ Drain,BPSG,Titanium Nitride Deposition: A sputterer is used to deposit TiN to a thickness of about 200A. This layer will help the subsequent tungsten