AT24C16B-.pdf
《AT24C16B-.pdf》由会员分享,可在线阅读,更多相关《AT24C16B-.pdf(12页珍藏版)》请在得力文库 - 分享文档赚钱的网站上搜索。
1、?1996 Microchip Technology Inc.DS21081D-page 1FEATURES?Single supply with operation from 4.5-5.5V?Low power CMOS technology-1 mA active current typical-10 A standby current typical at 5.5V?Organized as 4 or 8 blocks of 256 bytes(4 x 256 x 8)or(8 x 256 x 8)?2-wire serial interface bus,I2C?compatible?
2、Schmitt trigger,?ltered inputs for noise suppres-sion?Output slope control to eliminate ground bounce?100 kHz compatibility?Self-timed write cycle(including auto-erase)?Page-write buffer for up to 16 bytes?2 ms typical write cycle time for page-write?Hardware write protect for entire memory?Can be o
3、perated as a serial ROM?ESD protection 4,000V?1,000,000 ERASE/WRITE cycles guaranteed?Data retention 200 years?8-pin DIP,8-lead or 14-lead SOIC packages?Available for extended temperature rangeDESCRIPTIONThe Microchip Technology Inc.24C08B/16B is an 8K or16K bit Electrically Erasable PROM intended f
4、or use inextended/automotive temperature ranges.The deviceis organized as four or eight blocks of 256 x 8-bit mem-ory with a 2-wire serial interface.The 24C08B/16B alsohas a page-write capability for up to 16 bytes of data.The 24C08B/16B is available in the standard 8-pin DIPand both 8-lead and 14-l
5、ead surface mount SOIC pack-ages.-Automotive(E):-40?Cto+125?CPACKAGE TYPESBLOCK DIAGRAMNCSSCCA0A1NCA2NCV1234567141312NCSCLSDANC981110WPVNC14-lead SOIC24C08B/16B24C08B/16BA0A1A2VSS12348765VCCWPSCLSDA24C08B/16BA0A1A2VSS12348765VCCWPSCLSDAPDIP8-leadSOICHV GENERATOREEPROM ARRAYPAGE LATCHESYDECXDECSENSE
6、AMPR/W CONTROLMEMORYCONTROLLOGICI/OCONTROLLOGICWPSDASCLVCCVSS24C08B/16B8K/16K 5.0V I2C?Serial EEPROMsI2C is a trademark of Philips Corporation.This documentwascreatedwith FrameMaker4 0 4查询24C08 供应商24C08B/16BDS21081D-page 2?1996 Microchip Technology Inc.1.0ELECTRICAL CHARACTERISTICS1.1Maximum Ratings
7、*VCC.7.0VAll inputs and outputs w.r.t.VSS.-0.6V to VCC+1.0VStorage temperature.-65?C to+150?CAmbient temp.with power applied.-65?C to+125?CSoldering temperature of leads(10 seconds).+300?CESD protection on all pins.4 kV*Notice:Stresses above those listed under“Maximum ratings”may cause permanent dam
8、age to the device.This is a stress rat-ing only and functional operation of the device at those or anyother conditions above those indicated in the operational listingsof this speci?cation is not implied.Exposure to maximum ratingconditions for extended periods may affect device reliability.TABLE 1-
9、1:PIN FUNCTION TABLENameFunctionVSSGroundSDASerial Address/Data I/OSCL Serial ClockWPWrite Protect InputVCC+4.5V to 5.5V Power SupplyA0,A1,A2No Internal ConnectionTABLE 1-2:DC CHARACTERISTICSFIGURE 1-1:BUS TIMING START/STOPVCC=+4.5V to+5.5VAutomotive(E):Tamb=-40?C to+125?CParameterSymbolMinMaxUnitsC
10、onditionsWP,SCL and SDA pins:High level input voltageVIH.7 VccVLow Level input voltageVIL.3 VCCVHysteresis of Schmitt trigger inputsVHYS.05 VccV(Note)Low level output voltageVOL.40VIOL=3.0 mA,VCC=4.5VInput leakage currentILI-1010 AVIN=.1V to VCCOutput leakage currentILO-1010 AVOUT=.1V to VCCPin capa
11、citance(all inputs/outputs)CIN,COUT10pFVCC=5.0V(Note 1)Tamb=25?C,FCLK=1 MHzOperating currentICC writeICC read31mAmAVCC=5.5V,SCL=400 kHzStandby currentICCS100 AVCC=5.5V,SDA=SCL=VCCNote:This parameter is periodically sampled and not 100%tested.TSU:STATHD:STAVHYSTSU:STOSTARTSTOPSCLSDA?1996 Microchip Te
12、chnology Inc.DS21081D-page 324C08B/16BTABLE 1-3:AC CHARACTERISTICSFIGURE 1-2:BUS TIMING DATAParameterSymbolMinMaxUnitsRemarksClock frequencyFCLK100kHzClock high timeTHIGH4000nsClock low timeTLOW4700nsSDA and SCL rise timeTR1000ns(Note1)SDA and SCL fall timeTF300ns(Note 1)START condition hold timeTHD
13、:STA4000nsAfter this period the?rst clock pulse is generatedSTART condition setup timeTSU:STA4700nsOnly relevant for repeated START conditionData input hold timeTHD:DAT0nsData input setup timeTSU:DAT250nsSTOP condition setup timeTSU:STO4000nsOutput valid from clockTAA3500ns(Note 2)Bus free timeTBUF4
14、700nsTime the bus must be free before a new transmission can startOutput fall time from VIHmin to VIL maxTOF250ns(Note 1),CB 100 pFInput?lter spike suppres-sion(SDA and SCL pins)TSP50ns(Note 3)Write cycle timeTWR10msByte or Page modeEndurance24C08B24C16B1M10Mcycles25 C,VCC=5.0V,Block Mode(Note 4)Not
15、e 1:Not 100%tested.CB=total capacitance of one bus line in pF.2:As a transmitter,the device must provide an internal minimum delay time to bridge the unde?ned region(minimum 300 ns)of the falling edge of SCL to avoid unintended generation of START or STOP conditions.3:The combined TSP and VHYS speci
16、?cations are due to new Schmitt trigger inputs which provide improved noise and spike suppression.This eliminates the need for a TI speci?cation.4:This parameter is not tested but guaranteed by characterization.For endurance estimates in a speci?c appli-cation,please consult the Total Endurance Mode
17、l which can be obtained on our BBS or website.TSU:STATFTLOWTHIGHTRTHD:DATTSU:DATTSU:STOTHD:STATBUFTAATAATSPTHD:STASCLSDAINSDAOUT24C08B/16BDS21081D-page 4?1996 Microchip Technology Inc.2.0FUNCTIONAL DESCRIPTIONThe 24C08B/16B supports a Bi-directional 2-wire busand data transmission protocol.A device
18、that sendsdata onto the bus is de?ned as transmitter,and a devicereceiving data as receiver.The bus has to be controlledby a master device which generates the serial clock(SCL),controls the bus access,and generates theSTART and STOP conditions,while the 24C08B/16Bworks as slave.Both,master and slave
19、 can operate astransmitter or receiver but the master device deter-mines which mode is activated.3.0BUS CHARACTERISTICSThe following bus protocol has been de?ned:?Data transfer may be initiated only when the bus is not busy.?During data transfer,the data line must remain stable whenever the clock li
20、ne is HIGH.Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.Accordingly,the following bus conditions have beende?ned(Figure 3-1).3.1Bus not Busy(A)Both data and clock lines remain HIGH.3.2Start Data Transfer(B)A HIGH to LOW transition of the SDA
21、line while theclock(SCL)is HIGH determines a START condition.Allcommands must be preceded by a START condition.3.3Stop Data Transfer(C)A LOW to HIGH transition of the SDA line while theclock(SCL)is HIGH determines a STOP condition.Alloperations must be ended with a STOP condition.3.4Data Valid(D)The
22、 state of the data line represents valid data when,after a START condition,the data line is stable for theduration of the HIGH period of the clock signal.The data on the line must be changed during the LOWperiod of the clock signal.There is one clock pulse perbit of data.Each data transfer is initia
23、ted with a START conditionand terminated with a STOP condition.The number ofthe data bytes transferred between the START andSTOP conditions is determined by the master deviceand is theoretically unlimited,although only the last 16will be stored when doing a write operation.When anoverwrite does occu
24、r it will replace data in a?rst in?rstout fashion.3.5AcknowledgeEach receiving device,when addressed,is obliged togenerate an acknowledge after the reception of eachbyte.The master device must generate an extra clockpulse which is associated with this acknowledge bit.The device that acknowledges,has
25、 to pull down theSDA line during the acknowledge clock pulse in such away that the SDA line is stable LOW during the HIGHperiod of the acknowledge related clock pulse.Ofcourse,setup and hold times must be taken intoaccount.During reads,a master must signal an end ofdata to the slave by NOT generatin
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- AT24C16B
限制150内