先进芯片封装知识介绍.pptx
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1、OutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage第1页/共34页Package Development Trend第2页/共34页SOFamilyQFPFamilyBGAFamilyPackage Development Trend第3页/共34页CSPFamilyMemoryCardSiPModulePackage Development Trend第4页/共34页3D Package3DPackage第5页/共34页3D Package IntroductionetCSPStackFunctionalIntegrati
2、onHighLowTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP3S-CSPS-etCSPetCSP+S-CSPPS-fcCSP+SCSPPoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP5SCSPSS-SCSP(p
3、aste)UltrathinStackD2D3D4D2D2D3D4D2PoPQFN4SS-SCSP第6页/共34页Stacked DieTopdieBottomdieFOWmaterilWire第7页/共34页TSVTSV(ThroughSiliconVia)Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits
4、.A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace.Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbet
5、weenthechips.Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSV第8页/共34页WhatsPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.P
6、oP第9页/共34页PoPPS-vfBGAPS-etCSPLowLoopWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnology第10页/共34页PoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdies
7、ize/packagesizeratioCompatiblewithflipchip,wirebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutionsAmkorsTMVPoPTopviewBottomviewThroughMoldVia第11页/共34页PoPBallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)LaserdrillingSingulationFinalVisua
8、lInspectionBaseMtlThermaleffectProcessFlowofTMVPoP第12页/共34页Digital(Btm die)+Analog(Middle die)+Memory(Top pkg)Potable Digital GadgetCellular Phone,Digital Still Camera,Potable Game UnitMemorydieAnalogdieDigitaldiespacerEpoxyPiP第13页/共34页EasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThi
9、nnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformatIthasstandardballsizeandpitchConstructedwith:FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulationWhyPiP?PiP第14页/共34页MaterialforHighReliabilityBasedonLowWarpageWaferThinningFineProcessControlTop
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