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1、 芯片设计经理岗位职责 模拟混合芯片设计 经理 瀚芯询问 上海瀚芯商务询问有限公司,瀚芯询问,瀚芯 模拟混合芯片设计经理 (欧美公司,有海外出差及工作时机) Design Manager - Analog and Mix Signal Location: Zhangjiang, Shanghai Key Areas of Responsibilities: Lead analog mixed signal IP and chip projects in following areas Audio circuits Data converters PLLs and oscillators Fil
2、ters and amplifiers Voltage and current references LDOs and other power management circuits DC/DC converters I/Os and ESD protection Lead Analog and Mixed Signal team Manage Analog and Mix Signal group which includes design, verification, layout, and validation Manage projects with US team either as
3、 chip and Analog and Mix Signal block lead, and willing to travel when needed (typically 2-3 times per year). Manage outside suppliers of design services Required Skills and Attributes: BS in Electrical Engineering, or equivalent 7 + years, with 2+ years in a leadership role Deep knowledge of analog
4、 and mix signal design flows, analog circuits design, and transistor level layout Skilled in timing analysis, low power design, and tape-out Experience with Hspice and Cadence schematic tools Scripting for data manipulation and presentation such as using Perl/TCL/Shell Post-silicon validation experi
5、ence including bench debugging ability Successful group manager in team building, development, and retention Successful project management experience with effective and proactive interpersonal and communication skills and an ownership mindset Motivated team player with customer and quality focus Tec
6、hnical capability to work independently and hands-on as a self-starter Analytical and persistent in resolving technical issues. Possess strong work ethics with honesty and integrity 篇2:芯片设计师岗位职责 芯片前端设计师 职责描述: 负责芯片设计工程中数字前端设计开发工作,包括文档编写,RTL编码、形式验证、综合时序验证等工作,实现芯片功能、性能要求等; 任职要求: 1.电子工程,微电子相关专业本科及以上学历;3
7、年以上前端设计开发工作阅历; 2.熟识ASIC设计流程,娴熟使用Verilog,娴熟使用各种EDA工具,熟识规律综合工具等; 3.有丰富的顶层设计和前端IP集成阅历优先;有算法开发阅历,可高效的实现算法到AISC映射者优先; 4.熟识PCIeAXI等协议,内部总线互联设计及深度学习背景者优先; 5.具有良好的沟通力量和团队合作精神。 有丰富的顶层设计和前端IP集成阅历优先;有算法开发阅历,可高效的实现算法到AISC映射者优先; 职责描述: 负责芯片设计工程中数字前端设计开发工作,包括文档编写,RTL编码、形式验证、综合时序验证等工作,实现芯片功能、性能要求等; 任职要求: 1.电子工程,微电子相关专业本科及以上学历;3年以上前端设计开发工作阅历; 2.熟识ASIC设计流程,娴熟使用Verilog,娴熟使用各种EDA工具,熟识规律综合工具等; 3.有丰富的顶层设计和前端IP集成阅历优先;有算法开发阅历,可高效的实现算法到AISC映射者优先; 4.熟识PCIeAXI等协议,内部总线互联设计及深度学习背景者优先; 5.具有良好的沟通力量和团队合作精神。
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