《设计秒表-数字系统现场集成技术课程设计.docx》由会员分享,可在线阅读,更多相关《设计秒表-数字系统现场集成技术课程设计.docx(76页珍藏版)》请在得力文库 - 分享文档赚钱的网站上搜索。
1、深 圳 大 学 实 验 报 告 课程名称: 数字系统现场集成技术 实验项目名称: 设计秒表 学院: 信息工程学院 专业: 集成电路设计与集成系统 指导教师: 报告人: 学号: 班级: 实验时间: 实验报告提交时间: 教务部制76 目录一、 实验要求 -3二、 实验环境 -3三、 Nexys2开发板介绍及本实验功能说明 -3四、 框架图功能与ASM图 -4五、 各层VHDL代码、仿真结果及结果分析 -6六、 资源报告及实验结果 -50七、 问题及解决 -51八、 总结 -52一、实验要求:基本要求:它具有计时功能。此秒表有两个按键(reset, start)按下reset键后,秒表清零,按下st
2、art键后,开始计时, 再次按下start键后, 停止计时, 用FPGA开发板上的两个七段数码管显示时间(以秒为单位),计时由0 到 59 循环。高级要求(可选):实现基本要求的前提下,增加一个按键(select),用于轮流切换两个七段数码管分别显示百分之一秒,秒,分钟。二、实验环境1、 windows72、 ISE14.43、 Nexys2开发板三、Nexys2开发板介绍及本实验功能说明Nexys2开发板的核心芯片是具有1200K门的Spartan 3E FPGA,时钟是由50MHz的晶振提供,还有4个的7段数码管,4个按钮,8个拨码开关。下图为Nexys2开发板的实际部分板分布: 图3.1
3、 Nexys2开发板的实际部分板分布 图3.2 Nexys2开发板的I/O原理图Nexys2板上7段数码管为共阳极的方式,阴极独立。也就是说驱动7段数码管的每一段的显示,必须给低电平。由于板上的7段数码管的设计结构,为了在4个数码管上显示数字,必须给出扫描控制电路,图3.3给出了扫描控制电路的时序结构。为了在每个数码管上显示和连续的点亮数码管,所有的四个数码管应该每1到16ms就被驱动一次。 图3。3 时序结构但在本实验中,四个数码管的驱动时间为100us,所以每400us,数码管就被驱动一次,并且效果也很好。四、框架图功能与ASM图1、框架: 图4.1.1 框架本实验中使用了4个数码管、3个
4、按钮、5个拨动开关,数码管用来显示时间,按钮分别是rst_p异步复位按键、start_stop开始/暂停按键、record_button记录时间按键(只能记录最近的4次),拨动开关作用分别是key1(两位)秒表时间选择(00表示显示秒和百分秒、01表示显示分和秒、10表示显示时和分、11表示显示天和时)、mode可切换看秒表还是记录(1表示数码管显示的是正在计数时间,0表示数码管显示的是已记录的时间)、key2(两位)记录次数选择(00表示最近的一次记录时间、01表示最近第二次的记录时间、11表示最近第三次的记录时间、10表示最近第四次的记录时间)。2、 ASM图本实验中有一个counter计
5、数模块,输出想要的天、时、分、秒和百分秒(后面有详细介绍),它的ASM图如下: 图4.2 counterASM图五、各层VHDL代码、仿真结果及结果分析全部的模块展开如下: 图5.0 全部模块展开图1、 顶层chronography模块此模块只是负责连线、分频器的分频系数和复位的取反(因为我习惯低复位,而开发板的按键按下是高电平)代码为:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity chronography isport(clk : in std_logic;rst_p : in std_logic;start_stop : in std_lo
6、gic;record_button : in std_logic;key1 : in std_logic_vector (1 downto 0);-秒表时间选择mode : in std_logic;-可切换看秒表还是记录key2 : in std_logic_vector (1 downto 0);-记录次数选择seg7 : out std_logic_vector (7 downto 0);-dp,g,f,e,d,c,b,aan : out std_logic_vector (3 downto 0);end chronography;architecture Behavioral of c
7、hronography is-component button isport(clk : in std_logic;rst_n : in std_logic;start_stop : in std_logic;-继续/暂停键record_button : in std_logic;-记录键key1 : in std_logic_vector (1 downto 0);-时间切换选择mode : in std_logic;-选择秒表时间还是看记录时间key2 : in std_logic_vector (1 downto 0);-可记录4次,查看第几次记录time_sel : out std_l
8、ogic_vector (1 downto 0);-等于key1en_counter : out std_logic;-使能计数器,可使计数器继续或暂停en_recorder : out std_logic;-记录的使能,每按一次,就记录当下时间transfer : out std_logic;-选择秒表时间还是看记录时间record_sel : out std_logic_vector (1 downto 0)-可记录4次,查看第几次记录);end component;-component div_clk isgeneric (cnt : integer);-分频系数 port( clk :
9、 IN std_logic; rst_n : IN std_logic; f_clk : out std_logic ); end component;-component counter isport(clk : in std_logic;-100hzrst_n : in std_logic;en : in std_logic;dayten : out integer range 0 to 3;-天数十位dayge : out integer range 0 to 9;-天数个位hourten : out integer range 0 to 2;-小时十位hourge : out inte
10、ger range 0 to 9;-小时个位minten :out integer range 0 to 5;-分钟十位minge :out integer range 0 to 9;-分钟个位secten :out integer range 0 to 5;-秒十位secge :out integer range 0 to 9;-秒个位msecten : out integer range 0 to 9;-为100msmsecge : out integer range 0 to 9-为10ms);end component;-component mux10_4 isport(dayten
11、: in integer range 0 to 3;dayge : in integer range 0 to 9;hourten : in integer range 0 to 2;hourge : in integer range 0 to 9;minten : in integer range 0 to 5;minge : in integer range 0 to 9;secten : in integer range 0 to 5;secge : in integer range 0 to 9;msecten : in integer range 0 to 9;msecge : in
12、 integer range 0 to 9;sel : in std_logic_vector (1 downto 0);out1 : out integer range 0 to 9;out2 : out integer range 0 to 9;out3 : out integer range 0 to 9;out4 : out integer range 0 to 9);end component;-component seg7display isport(clk : in std_logic;rst_n : in std_logic;shu1 : in integer range 0
13、to 9;shu2 : in integer range 0 to 9;shu3 : in integer range 0 to 9;shu4 : in integer range 0 to 9;seg7 : out std_logic_vector (7 downto 0);an : out std_logic_vector (3 downto 0);end component;-component recorder isport(clk : in std_logic;en_recorder : in std_logic;transfer : in std_logic;record_sel
14、: in std_logic_vector (1 downto 0);daytenin : in integer range 0 to 3;-天数十位daygein : in integer range 0 to 9;-天数个位hourtenin : in integer range 0 to 2;-小时十位hourgein : in integer range 0 to 9;-小时个位mintenin :in integer range 0 to 5;-分钟十位mingein :in integer range 0 to 9;-分钟个位sectenin :in integer range 0
15、 to 5;-秒十位secgein :in integer range 0 to 9;-秒个位msectenin : in integer range 0 to 9;-为100msmsecgein : in integer range 0 to 9;-为10msdayten : out integer range 0 to 3;-天数十位dayge : out integer range 0 to 9;-天数个位hourten : out integer range 0 to 2;-小时十位hourge : out integer range 0 to 9;-小时个位minten :out i
16、nteger range 0 to 5;-分钟十位minge :out integer range 0 to 9;-分钟个位secten :out integer range 0 to 5;-秒十位secge :out integer range 0 to 9;-秒个位msecten : out integer range 0 to 9;-为100msmsecge : out integer range 0 to 9-为10ms);end component;-signal clk_10khz, clk_100hz: std_logic;signal rst_n : std_logic;sig
17、nal time_sel : std_logic_vector (1 downto 0);signal en_counter : std_logic;signal en_recorder : std_logic;signal recorder_sel : std_logic_vector (1 downto 0);signal transfer : std_logic;-cr : counter_recordersignal dayten_cr : integer range 0 to 3 := 0;signal dayge_cr : integer range 0 to 9 := 0;sig
18、nal hourten_cr : integer range 0 to 2 := 0;signal hourge_cr : integer range 0 to 9 := 0;signal minten_cr : integer range 0 to 5 := 0;signal minge_cr : integer range 0 to 9 := 0;signal secten_cr : integer range 0 to 5 := 0;signal secge_cr : integer range 0 to 9 := 0;signal msecten_cr : integer range
19、0 to 9 := 0;signal msecge_cr : integer range 0 to 9 := 0;signal dayten : integer range 0 to 3 := 0;signal dayge : integer range 0 to 9 := 0;signal hourten : integer range 0 to 2 := 0;signal hourge : integer range 0 to 9 := 0;signal minten : integer range 0 to 5 := 0;signal minge : integer range 0 to
20、 9 := 0;signal secten : integer range 0 to 5 := 0;signal secge : integer range 0 to 9 := 0;signal msecten : integer range 0 to 9 := 0;signal msecge : integer range 0 to 9 := 0;signal shu1 : integer range 0 to 9 := 0;signal shu2 : integer range 0 to 9 := 0;signal shu3 : integer range 0 to 9 := 0;sign
21、al shu4 : integer range 0 to 9 := 0;beginprocess(rst_p)beginrst_n = not rst_p;end process;-产生10khz的时钟,用于useg7displayuclk_10khz : div_clk generic map (5000) port map(clk, 1, clk_10khz);-产生200hz的时钟,用于button和counteruclk_100hz : div_clk generic map (500000) port map(clk, rst_n, clk_100hz);-扫面按键u1button
22、: button port map(clk_100hz, rst_n, start_stop, record_button, key1, mode, key2, time_sel, en_counter, en_recorder, transfer, recorder_sel);-计数器,可输出天数、小时、分钟、秒以及10毫秒u1counter : counter port map(clk_100hz, rst_n, en_counter, dayten_cr, dayge_cr, hourten_cr, hourge_cr, minten_cr, minge_cr, secten_cr, s
23、ecge_cr, msecten_cr, msecge_cr);-记录器,可记录最新4次u1recorder : recorder port map(clk_100hz, en_recorder, transfer, recorder_sel, dayten_cr, dayge_cr, hourten_cr, hourge_cr, minten_cr, minge_cr, secten_cr, secge_cr, msecten_cr, msecge_cr, dayten, dayge, hourten, hourge, minten, minge, secten, secge, msecte
24、n, msecge);-因为只有四个数码管,所以要选择显示什么时间u1mux10_4 : mux10_4 port map(dayten, dayge, hourten, hourge, minten, minge, secten, secge, msecten, msecge, time_sel, shu1, shu2, shu3, shu4);-数码管的显示useg7display : seg7display port map(clk_10khz, rst_n, shu1, shu2, shu3, shu4, seg7, an);end Behavioral;RTL原理图为: 图5.1.1
25、 顶层RTL原理图打开之后可以看到有七个子模块: 图5.1.2 顶层RTL原理图2、 button模块此模块是按键和拨动开关扫描,用来缓存和解析I/O输入的数据,即是按键和拨动开关的数据,还可以有一定程度的消抖。代码为:ibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;entity button isport(clk : in std_logic;rst_n : in std_logic;start_stop : in std_logic;-继续/暂停键record_button : in std_logic;-记录键key1 : in std_logic_vec
26、tor (1 downto 0);-时间切换选择mode : in std_logic;-选择秒表时间还是看记录时间key2 : in std_logic_vector (1 downto 0);-可记录4次,查看第几次记录time_sel : out std_logic_vector (1 downto 0);-等于key1en_counter : out std_logic;-使能计数器,可使计数器继续或暂停en_recorder : out std_logic;-记录的使能,每按一次,就记录当下时间transfer : out std_logic;-选择秒表时间还是看记录时间record
27、_sel : out std_logic_vector (1 downto 0)-可记录4次,查看第几次记录);end button;architecture Behavioral of button isbeginprocess(clk, rst_n)variable start_stop1 : std_logic := 0;variable start_stop2 : std_logic := 0;variable start_stop3 : std_logic := 0;variable recordbutton1 : std_logic := 0;variable recordbutt
28、on2 : std_logic := 0;variable recordbutton3 : std_logic := 0;beginif(rst_n = 0) thenstart_stop1 := 0;start_stop2 := 0;start_stop3 := 0;recordbutton1 := 0;recordbutton2 := 0;recordbutton3 := 0;elseif(clk event and clk = 1) thenstart_stop2 := start_stop1;start_stop1 := start_stop;recordbutton2 := reco
29、rdbutton1;recordbutton1 := record_button;if(start_stop1 = 0) and (start_stop2 = 1) then-下降沿start_stop3 := not start_stop3;end if;if(recordbutton1 = 1) and (recordbutton2 = 0) thenrecordbutton3 := 1;elserecordbutton3 := 0;end if;time_sel = key1;transfer = mode;record_sel = key2;end if;end if;en_count
30、er = start_stop3;en_recorder 0); signal mode : std_logic := 0; signal key2 : std_logic_vector(1 downto 0) := (others = 0); -Outputs signal time_sel : std_logic_vector(1 downto 0); signal en_counter : std_logic; signal en_recorder : std_logic; signal transfer : std_logic; signal record_sel : std_logi
31、c_vector(1 downto 0); - Clock period definitions constant clk_period : time := 10 ns; BEGIN - Instantiate the Unit Under Test (UUT) uut: button PORT MAP ( clk = clk, rst_n = rst_n, start_stop = start_stop, record_button = record_button, key1 = key1, mode = mode, key2 = key2, time_sel = time_sel, en_
32、counter = en_counter, en_recorder = en_recorder, transfer = transfer, record_sel = record_sel ); - Clock process definitions clk_process :process beginclk = 0;wait for clk_period/2;clk = 1;wait for clk_period/2; end process; - Stimulus process stim_proc1: process begin - hold reset state for 100 ns.
33、rst_n = 1;start_stop = 0;record_button = 0; wait for 30 ns;start_stop = 1;wait for 30 ns;start_stop = 0;wait for 100 ns;record_button = 1;wait for 30 ns;record_button = 0; wait for 100 ns;start_stop = 1;wait for 30 ns;start_stop = 0; - insert stimulus here wait; end process;stim_proc2: process begin - hold reset state for 100 ns.key1 = 00;mode = 0;key2 = 10;wait for 50 ns;key1 = 01;mode = not mode;key2 = 11;wait for 50 ns;key1 = 10;mode = not mode;key2 = 00;wait for 50 ns;key1 = 11;mode = not mode;key2 = 01
限制150内