E1107053241原版完整文件.docx
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1、Dilip K, et. al. International Journal of Engineering Research and Applications ISSN: 2248-9622, Vol. 11, Issue 7, (Series-V) July 2021, pp. 32-41RESEARCH ARTICLEOPEN ACCESSDesign and Verification of AHB Protocol Using System Verilog and Universal Verification Methodology (UVM)Dilip K*, Vijaya Praka
2、sh A M* M.Tech, Department of ECE, Bangalore Institute of Technology, Karnataka, India* Professor Department of ECE, Bangalore Institute of Technology, Karnataka, IndiaABSTRACT :Recently, VLSI technology has improved significantly and more transistors can be incorporated in a chip. A System on-Chip
3、(SOC) Configuration have number of blocks are integrated on a single chip. Numerous blocks are integrated in single IC, but to access their function, they requires a powerful communication architecture. This can only be achieved by using on-chip bus architecture to meet their requirements. Different
4、 Companies has various on-Chip Bus architectures but one of the most suitable architecture is AMBA by ARM. AMBA consist of three buses, namely, Advanced System Bus (ASB), Advanced Peripheral Bus (APB) and Advanced High Performance Bus (AHB).when compared to other two buses AHB is high performance, h
5、igh bandwidth and for high clock frequency system modules the System designers select AHB as their primary choice. The AHB (Advanced High-performance Bus) is a superior bus in AMBA (Advanced Microcontroller Bus Architecture) family. It is a norm for intercommunication of modules in a framework. The
6、AHB (Advance High performance) bus Standards are characterized by ARM which supports for the communication of on-chip memories, processors and interfaces of external off-chip memory. Here the basic blocks such as master, slave, decoder, and arbiter are used to design and verify an AHB that supports
7、multiples master and multiples slave. The conventional way of verification is simulation based. As the Technology improves the complexity of ICs has been increased. Thus, time spent on verification has also been increased. The main focus is to design of AHB protocol in Verilog and verify using Hardw
8、are verification language such as System Verilog and standard Methodology such as Universal Verification Methodology (UVM). QuestaSim (Advanced verification tool from Mentor Graphics) is an EDA tool used to simulate and verify the design and obtain Coverage report.Keywords AMBA, AHB, APB, ASB, OCB,
9、SOC, UVMDate of Submission: 10-07-2021Date of Acceptance: 26-07-2021DOI: 10.9790/9622-110705324140 | P a g eI. INTRODUCTION1.1 About AMBA busThe AMBA is an Advanced Microcontroller Bus Architecture defined by ARM, it is an open standard widely used for an on-chip bus system. The standard is intends
10、to simplify the component design by allowing the use of interchangeable parts the within the SoC style. It promotes the use of holding parts, so that a minimum of a neighborhood of the SoC can be reconstructed, instead of having to rewrite it entirely each time. AHB (Advanced High-performance Bus),
11、ASB (Advanced System Bus), and APB (Advanced Peripheral Bus) are the bus groups defined in the AMBA AHB. The AHB is employed for high- performance, high frequency architecture. These applications includes are ARM cores and high-speed RAM inside the system, Nand Flash, DMA and Bridge links. 1 The APB
12、 is used for connecting external devices such as UART, keypad and timer, and has low performance requirements, while it isused for optimizing power consumption. AMBA is the Standard bus-based microcontroller typical feature a high-performance system hub bus (AHB or ASB) that supports for external me
13、mory bandwidth, including CPUs, on-chip memories, and other direct data access (DMA) devices. For most of the transmission between various units, such as CPUs, on-chip memories, and DMA, the bus serves as a high bandwidth interface.Fig.1: AMBA bus Block Diagram1.2 Advance System Bus (ASB)The ASBs (A
14、dvanced system buses) are used for defining high performance buses that can be used in embedded microcontrollers with 16-bit and 32-bit architecture. An ASB provides a high performance pipelined bus that can provide access to multiple masters. The Flow of essential operations of ASB is: Master commu
15、nicates with the bus. Arbiter observes masters status. Then, master begins communicating with the bus. The decoder uses the accurate address lines to choose a bus slave. Then, a signal is given back to the bus master by the slave.1.3 Advance Peripheral Bus (APB)The Advanced Peripheral Bus (APB) is u
16、tilized for connecting low bandwidth peripherals. APB is a simple non-pipelined protocol that can be utilized to communicate from a master to a multiple slaves for read and write through the shared bus. 5 The read and write bus shares the same set of signals and no burst data transfers are supported
17、.1.4 Advance High Performance Bus (AHB)An AHB bus is a latest generation of AMBA bus that is intended to handle the necessities addresses the prerequisites of high performance synthesizable design styles. It is a Standard system bus that supports multiple bus masters and provides high-bandwidth oper
18、ation. AMBA AHB implements the features needed for standard, high clock frequency systems including: Burst transfers. Single-cycle bus master relinquishing. Single-clock edge operation. Non-tristate implementation. Wider information bus configurations (32/128 bits).The AMBA AHB bus protocol is desig
19、ned using a central multiplexer interconnection design. By design, all bus masters transmit address and control signals indicating the data transfer they want to perform and the arbiter determines which master has its address and control signal based on that information it is provided to all of the
20、slaves. The decoder is used to control the read data and response signal from multiplexer, which chooses the proper signals from the slave that is engaged in the transfer.II. LITERATURE REVIEWDesign and verification of AMBA AHB bus which consist of one master and multiple slave designed in Verilog H
21、ardware descriptive language and shown the output for read and write operation.1 The Design under test is verified using thesystem Verilog environment and obtained the coverage report around 65%.This paper tells us the coverage report obtained is less. The Questa sim is the EDA tool used to obtain t
22、he simulation output.The paper presents a Method for Designing an efficient2 master interface and slave interface based on the finite state machines in Verilog hardware description language and used the Mentor graphics tool Model sim 10.03a to simulate and the synthesis of the design is performed in
23、 Xilinx ISE design tool. The completed AMBA AHB system is then inspected for proper lossless communication between master and slave interface. This article tells us does not used the verification language such as system Verilog.In this the efficient design of an AMBAcontroller is designed and tested
24、 3 for read and write operations using a Xilinx simulator. The read and write operations using AMBA are illustrated with simple examples.As reported in paper 4, The AHB master interface and arbiter interface are designed using the finite state machines in Verilog hardware description language and th
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